The present invention relates to a semiconductor device, and, more particularly, to a composite circuit which is a combination of a MOS (metal-oxide-semiconductor) transistor and a bipolar transistor, or a MOS-drive bipolar-output logic circuit.
Further, the present invention relates to a dynamic semiconductor memory comprising a dynamic memory cell using an insulated-gate field effect transistor and storage capacitance in a memory cell, and a driving circuit using a bipolar transistor having particularly high drivability and high noise immunity and being suitable to obtain pulse output amplitude higher than the supply voltage and an insulated-gate field effect transistor. Further, the invention relates to a method of generating control signals within a chip so that the dynamic memory performs normal operations.
In a semiconductor memory, in order to achieve high speed and high density simultaneously, a memory cell is constituted by an insulated-gate field effect transistor (hereinafter referred to as an "MIS transistor"), and peripheral circuits for transmitting or receiving signals with the memory cell include a bipolar transistor. Examples of the above-mentioned constitution are disclosed in Japanese Patent Application Laid-Open No. 129994/1980 and No. 58193/1981. In these patents, a flip-flop composed of four MIS transistors and two load-devices is used in a memory cell, and a so-called static memory is constituted. Consequently, the area of the memory cell is relatively large and constitution at high density is difficult. On the other hand, as shown in FIGS. 1A and 1B, in a dynamic memory cell using between one and three MIS transistors and storage capacitance for storing information `1`, `0` by the amount of the stored charges in the capacitance, the area of the memory cell is small and constitution at high density is favorable. In the semiconductor memory using the dynamic memory cell, however, since the memory cell does not have self reproduction capability of the stored information, read signals to the data line D must be amplified and then rewritten, and the potential of the data line D must be pre-charged to constant voltage before the reading. Consequently, in an actual dynamic memory, in order to perform a memory operation (e.g., read, write, hold), relatively complicated control is required in comparison to static memory arrangements. Accordingly, in the dynamic memory of the prior art,both the memory cell and the peripheral circuits are constituted using MIS transistors, and constitution is at high density but the speed is slow at the access time or the like.
On the other hand, Japanese Patent Application Laid-Open No. 75487/1984 describes that in a semiconductor memory where large current must be supplied to word line driving circuits such as a taper isolated dynamic RAM having a memory cell constituted by a MIS transistor with its drain/source connected between a bit line and a word line, use of a driving circuit comprising a bipolar transistor can achieve high density and high speed. Since the memory cell of the taper isolated dynamic RAM is constituted by one MIS transistor, it is favorable from the viewpoint of high density in comparison to the static RAM.
If the high density is further advanced holding the high speed, however, current flowing through the word line driving circuit increases and therefore the bipolar transistor used in the word line driving circuit must be of large size so as to hold high reliability, resulting in an increase of the chip area. Consequently, the merit of high density is deteriorated.
Further, Japanese Patent Application Laid-Open No. 25423/1984 discloses a driving circuit in the prior art. The driving circuit is shown in FIG. 1C, and operation and problems thereof will be described. The following description will be performed assuming that voltage Vss of a voltage supply 9 is 0 V. When voltage of an input terminal 1 is 0 V, a p-channel insulated gate field effect transistor 4 is turned on and current flows through the base of a first npn bipolar transistor 7 which is turned on. On the other hand, a second npn bipolar transistor 8 is not turned on because its base potential is 0 V. As a result, current flows through an output terminal 2, and potential of the output terminal 2 rises. The potential of the output terminal 2 becomes a value of voltage Vcc of a positive voltage supply 3 subtracted by base-emitter forward voltage V.sub.BE of the first npn bipolar transistor 7. If voltage of the input terminal 1 is changed to the positive supply voltage Vcc, since voltage of the output terminal 2 is V.sub.cc -V.sub.BE at first, the n-channel insulated gate field effect transistor 6 is turned on and current flows through the base of the second npn bipolar transistor 8 so as to lower the potential of the output terminal. On the other hand, since the p-channel insulated gate field effect transistor becomes cut-off, base current of the first npn bipolar transistor 7 does not flow and the n-channel insulated gate transistor 5 is turned on, whereby charge stored in the base of the first npn bipolar transistor 7 is discharged by the n-channel insulated gate field effect transistor and the npn bipolar transistor 7 rapidly becomes cut-off. As a result, potential of the output terminal 2 is rapidly lowered. Then the potential of the output terminal 2 is determined by threshold voltage Vth of the n-channel insulated gate transistor 6 and base-emitter forward voltage V.sub.BE of the second npn bipolar transistor 8, and becomes V.sub.BE +Vth. If the value becomes negative, the second npn bipolar transistor 8 is saturated and the high speed is deteriorated. Consequently, it is preferable that the value is set to become slightly positive taking into consideration variation in the manufacture condition of the semiconductor device, as described in the patent application.
The circuit in the prior art has a defect in that voltage amplitude of the output terminal cannot be made equal to the amount of the supply voltage. In order to eliminate the defect, flowing-in or flowing-out of current to the output terminal may be performed by insulated gate field effect transistors. In this case, in order to achieve the high speed in similar degree to that using the bipolar transistors, transistors having large channel length and width are required and therefore this method is unfavorable from the viewpoint of high density. As shown in FIG. 1D, either of the bipolar transistors may be displaced by an insulated gate field effect transistor as in the circuit constitution of Japanese Patent Application Laid-Open No. 35761/1973. Also in this case, however, it is clear that above-mentioned defect cannot be completely eliminated.
In summary, in the prior art arrangements, logical amplitude becomes small at the BiP side and the density is deteriorated at the MOS side.
Further in a circuit of the prior art as shown in FIG. 1C or FIG. 1D, if potential of the output terminal is abnormally varied, the variation cannot be absorbed. This aspect will be described referring to FIG. 1D. In FIG. 1D, assume that potential of the output terminal 11 is in a steady condition at a value of the voltage Vcc of the positive voltage supply 12 subtracted by the base/emitter forward voltage V.sub.BE of the npn bipolar transistor 15. Assume that abnormal potential variation is produced in the output terminal 11 by any cause. If the potential variation tends to lower the potential of the output terminal 11, the npn bipolar transistor 15 is turned on and the potential of the output terminal is restored. However, if the potential variation tends to raise the potential of the output terminal 11, the transistor 15 becomes cut-off. Furthermore, since the input terminal 10 is at 0 V, the N-channel insulated gate field-effect transistor 16 becomes cut-off and therefore the potential variation cannot be absorbed. Although the description has been performed regarding the case that the output terminal 11 is at high level, conditions are similar also in the case that the output terminal 11 is at low level. Furthermore, it is clear that a similar defect exists also in the circuit of FIG. 1C.
Accordingly, the above-described circuits in the prior art have defects in that the output amplitude is less than the amount of the supply voltage and potential of the output terminal is subject to variation.
A further discussion of the composite circuits which utilize a low power consumption of CMOS transistors and a high load drive capability of bipolar transistors will now be discussed.
One of those, which is shown in FIG. 72, is a circuit similar to one shown in FIG. 8 of the IEEE Transaction on Electron Devices, Vol. ED-16, No. 11, November 1969, page 950. In FIG. 72, numeral 301 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a base of an NPN transistor 303, and numeral 302 denotes an NMOS transistor having a drain thereof connected to an output terminal OUT, a gate thereof connected to the input terminal IN and a source thereof connected to a base of an NPN transistor 304. A collector of the NPN transistor 303 is connected to the power supply +V and an emitter thereof is connected to the output terminal OUT. A collector of the NPN transistor 304 is connected to the output terminal OUT and an emitter thereof is connected to a common potential point or a ground potential point GND.
The operation of the circuit is as follows. When the input terminal IN is at an "L" level, the NMOS transistor 302 is off and the NPN transistor 304 is also off. On the other hand, the PMOS transistor 301 is on and a base current is supplied to the NPN transistor 303 through the PMOS transistor 301. As a result, a charge current flows from the NPN transistor 303 to a load (not shown) and the output terminal OUT is switched to an "H" level. When the input terminal IN is at the "H" level, the PMOS transistor 301 is off and the NPN transistor 303 is also off. On the other hand, the NMOS transistor 302 is on and a base current is supplied to the NPN transistor 304 through the NMOS transistor 302 and the NPN transistor 304 is turned on. As a result, the charge stored in the load is discharged through the NPN transistor 304 and the output terminal OUT is switched to the "L" level. In this circuit, an output voltage level of the circuit is shifted by base-emitter voltages V.sub.BEQ1 and V.sub.BEQ2 of the NPN transistors 303 and 304. Thus, the "H" level is (+V-V.sub.SEQ1) and the "L" level is V.sub.BEQ2.
FIG. 302 shows a circuit similar to one disclosed in Japanese Patent Unexamined Publication No. 54-148469. In FIG. 73, numeral 305 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a junction point or node B of a base of an NPN transistor 307 and a base of a PNP transistor 308. Numeral 306 denotes an NMOS transistor having a drain thereof connected to said junction point, a gate thereof connected to the input terminal IN and a source thereof connected to a power supply -V. A collector of the NPN transistor 307 is connected to the power supply +V and an emitter thereof is connected to an output terminal OUT. An emitter of the PNP transistor 308 is connected to the output terminal OUT and a collector thereof is connected to the power supply -V.
In this circuit, an output voltage level is also shifted by base-emitter voltages V.sub.BEQ1 and V.sub.BEQ2 of the NPN transistor 307 and the PNP transistor 308. Thus, the "H" level is (+V-V.sub.BEQ1) and the "L" level is (-V+V.sub.BEQ2).
FIG. 74 shows a circuit similar to one disclosed in Japanese Unexamined Patent Application No. 52-26181. In FIG. 74, numeral 309 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a base of an NPN transistor 311. Numeral 310 denotes an NMOS transistor having a drain thereof connected to an output terminal OUT, a gate thereof connected to an input terminal IN and a source thereof connected to a power supply -V. A collector of the NPN transistor 311 is connected to the power supply +V and an emitter thereof is connected to the output terminal OUT.
In this circuit, an output voltage level is also shifted by base-emitter voltage V.sub.BEQ1 of the NPN transistor 311. Thus, the "H" level is (+V-V.sub.BEQ1) and the "L" level is -V.
In FIG. 75, numeral 312 denotes a symbol of a MOS-drive bipolar-output logic circuit having offsets at the output levels shown in FIGS. 72 to 74.
FIG. 76 shows a MOS-drive bipolar-output tri-state circuit 313 which is similar to the circuit of FIG. 20 disclosed in U.S. patent application Ser. No. 703,171 entitled "Arithmetic Operation Unit and Arithmetic Operation Circuit" filed Feb. 19, 1985 in the name of Hitachi, Ltd., based on Japanese Patent Applications Nos. 59-31257 filed on Feb. 20, 1984 and 60-2020 filed on Jan. 11, 1985. In the figure, numerals 314 and 315 denote series-connected PMOS transistors, a source of the PMOS 314 is connected to a power supply +V and a gate thereof is connected to an input terminal E. A gate of the PMOS transistor 315 is connected to an input terminal IN and a drain thereof is connected to a base of a NPN transistor 318. Numerals 316 and 317 denote series-connected NMOS transistors. A drain of the NMOS transistor 316 is connected to an output terminal OUT and a gate thereof is connected to the input terminal IN. A gate of the NMOS transistor 317 is connected to an input terminal E and a source thereof is connected to a base of an NPN transistor 319. A collector of the NPN transistor 318 is connected to the power supply +V and an emitter thereof is connected to the output terminal OUT. A collector of the NPN transistor 319 is connected to the output terminal OUT and an emitter thereof is connected to a ground GND, a load capacitor C.sub.L is connected to the output terminal OUT.
This circuit is a tri-state logic circuit and the output level is shifted. The operation is as follows.
When the input terminal E is at the "L" level and the input terminal E is at the "H" level, the PMOS transistor 314 and the NMOS transistor 317 are off, and the NPN transistor 318 and the NPN transistor 319 are also off. As a result, the output terminal OUT is in a high impedance state regradless of the level of the input terminal IN.
When the input terminal E is at the "H" level and the input level E is at the "L" level, the NMOS transistor 317 and the PMOS transistor 314 are on. If the input terminal IN is at the "L" level, the PMOS transistor 315 and the NPN transistor 318 are on and the output terminal OUT is charged to (+V-V.sub.BEQ1). If the input terminal IN is at the "H" level, the NMOS transistor 316 and the NPN transistor 319 are on and the output terminal OUT is discharged to +V.sub.BEQ2. Thus, this circuit functions as an inverter having an output "H" level thereof shifted down by V.sub.BEQ1 and an output "L" level thereof shifted up by V.sub.BEQ2.
In FIG. 77, numeral 320 denotes a symbol of the circuit of FIG. 76.
The MOS-bipolar composite circuits described above are different from a CMOS transistor buffer circuit in that they can switch a large capacitive load at a high speed and the output voltage level is shifted by the base-emitter voltage V.sub.BE of the bipolar transistor.
However, when such an output voltage level shifted signal is used as a gate drive signal of a MOS switch, the MOS switch may not be completely turned off in a certain circuit. A typical MOS switch circuit in which such a problem may arise is a well-known clocked inverter shown in FIG. 78. A numeral 321 in FIG. 79 denotes a symbol of FIG. 78.
In FIG. 78, numeral 322 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a source of a PMOS transistor 323. A gate of the PMOS transistor 323 is connected to a clock terminal .phi. and a drain thereof is connected to an output terminal OUT. Numeral 324 denotes an NMOS transistor having a drain thereof connected to the output terminal OUT, a gate thereof connected to a clock terminal .phi. and a source thereof connected to a drain of an NMOS transistor 325. A gate of the NMOS transistor 325 is connected to a common potential point GND, C.sub.s denotes connected to the input terminal IN and a source thereof a stray capacitance at the output terminal OUT.
The operation of this circuit is as follows. When .phi. is at the "H" level and .phi. is at the "L" level, the PMOS transistor 323 and the NMOS transistor 324 are on. If the input terminal IN is at the "L" level, the NMOS transistor 325 is off and the PMOS transistor 322 is on, and the stray capacitance CS is charged through the PMOS transistors 322 and 323 so that the output terminal OUT assumes the "H" level. On the other hand, if the input terminal IN is at the "H" level, the PMOS transistor 322 is off and the NMOS transistor 325 is on, and the charge stored in the stray capacitor C.sub.s is discharged through the NMOS transistors 324 and 325 so that the output terminal OUT assumes the "L" level.
When .phi. is at the "L" level and .phi. is at the "H" level, the PMOS transistor 223 and the NMOS transistor 324 are off. Thus, the level of the output terminal is held irrespective of the level of the input terminal IN. Thus, this circuit has a dynamic latch function.
However, when the clocks .phi. and .phi. are supplied from the prior art composite circuit shown in FIGS. 72 to 74 or the composite circuit shown in FIG. 76 which is not prior art, the operation in the hold state is as follows. Let us assume that the power supply +V is 5 volts, the "H" levels of .phi. and .phi. are 4.3 volts, the "L" levels thereof are 0.7 volt, the "H" level of the input terminal IN is 5 volts and the "L" level thereof is 0 volt.
When .phi.=0.7 volt, .phi.=4.3 volt and the output terminal OUT is held at the "H" level, the PMOS transistor 323 and the NMOS transistor 324 conduct slightly because the gate-source voltages thereof are not completely zero. If the input terminal IN is at the "L" level, the NMOS transistor 325 is off and the PMOS transistor 322 is on. Therefore, the output terminal OUT is held at the "H" level. If the input terminal IN is at the "H" level, the NMOS transistor 325 is on and the charge stored in the stray capacitor C.sub.S is discharged through the slightly conducting NMOS transistor 324 and the on NMOS transistor 325. As a result, the output terminal OUT is switched from the "H" level to the "L" level. Similarly, when the output terminal OUT is held at the "L" level and the input terminal IN is at the "L" level, the NMOS transistor 325 is off and the PMOS transistor 322 is on. As a result, the charge stored in the stray capacitor C.sub.S is charged through the PMOS transistor 322 which is now in on state and the slightly conducting PMOS transistor 323 so that the output terminal OUT is switched from the "L" level to the "H" level.
Thus, in the prior art composite circuits, the output terminal OUT is not completely "L" level, that is, the level of the output terminal OUT does not completely reach the common potential or the lower potential of the power supply when the output terminal OUT is at the "L" level, and the output terminal OUT is not completely "H" level, that is, the level of the output terminal does not reach the higher potential of the power supply when the output terminal OUT is at the "H" level. This adversely affects to the succeeding stage circuit.
In a circuit shown in Japan Patent Unexamined Publication No. 59-205828 (FIG. 4 in particular), a logic circuit which is a composite circuit comprising MOS transistors and bipolar transistor and another logic circuit comprising MOS transistors and having the same function as the first logic circuit are connected in parallel so that the output signal level completely reach the "L" or "H" level. In this circuit, since an input capacitance is larger than that of a logic circuit which comprises only the composite circuit, an operation speed of a preceding circuit to drive the logic circuit is lower and hence an overall speed is reduced. Furthermore, in a multi-input buffer circuit, the number of elements required for the parallel MOS logic circuit increases in proportion to the number of inputs.
Reference may be made to U.S. patent application Ser. No. 680,495 filed Dec. 11, 1984 in the name of Hitachi, Ltd., and to Japanese Patent Unexamined Publication No. 59-205828.